1.Field of the Invention
The present invention relates to a driving circuit for outputting a video signal to a data signal line, the driving circuit being used in a display apparatus such as an active matrix liquid crystal display apparatus or the like.
2.Description of the Related Art
In an active matrix liquid crystal display apparatus, an image is displayed by driving pixels formed in a matrix each by a switching device such as a thin film transistor. A conventional active matrix liquid crystal display apparatus is a driver monolithic display apparatus, in which a display section having pixels and a data signal line driving circuit (hereinafter, referred to as "source driver") for driving the pixels are formed on a single substrate. In the driver monolithic display apparatus, since the switching devices and the source driver are formed in an identical step of production, the switching devices and a device forming the source driver desirably have an identical structure with each other. In a transparent display apparatus, a switching device should be formed on a transparent substrate formed of, for example, silica glass by use of a thin film process, and further a device forming a source driver should have a necessary operating speed. For these reasons, a polysilicon thin film transistor (hereinafter, referred to as "polysilicon TFT") is usually used for both the switching device and the device forming the source driver.
The polysilicon TFT has a mobility of approximately 10 to 100 cm.sup.2 /V.s. Accordingly, the maximum stable operating speed which has been realized so far in a shift register using such a polysilicon TFT is several megahertz. However, in a display apparatus having a large number of pixels, for example, a NTSC-TV (National Television System Committee television) having 720 horizontal pixels, a shift register forming a source driver should have an operating speed of 14.4MHz. In order to bridge such a difference, a source driver which accommodates the lower operating speed of a shift register is used.
FIG. 12 illustrates a structure of such a source driver. The source driver includes four shift registers 11 to 14, sampling analog switches 21 to 2n controlled to be "ON" or "OFF" by the shift registers 11 to 14, a video signal line 30 to which a video signal Video is sent, and sampling capacitors 41 to 4n connected to the video signal line 30 through the sampling analog switches 21 to 2n. Data signal lines S1 to Sn connected to pixels (not shown) are branched to be connected to the sampling analog switches 21 to 2n, and the sampling capacitors 41 to 4n. The data signal lines S1 to Sn are divided into groups each including adjacent four data signal lines (for example, S1, S2, S3 and S4). The four data signal lines of each group are respectively connected to the sampling analog switches connected to the shift registers 11 to 14. Practically, every first data signal line of each group (for example, S1, S5, S9, . . . ) are connected to the shift register 11. Every second data signal line of each group (for example, S2, S6, . . . ) are connected to the shift register 12. Every third data signal line of each group (for example, S3, S7, . . . ) are connected to the shift register 13. Every fourth data signal line of each group (for example, S4, S8, . . . ) are connected to the shift register 14.
The sampling analog switches 21 to 2n are provided for sampling a video signal Video sent to the video signal line 30. The sampling capacitors 41 to 4n are provided for retaining the video signal Video sampled by the sampling analog switches 21 to 2n, respectively.
The operation of the source driver having the above-mentioned structure will be described with reference to FIG. 13. The start of the four shift registers 11 to 14 is controlled by a shift start pulse SP which is common to the four shift registers 11 to 14. The shift registers 11 to 14 are controlled by a pair of shift clocks having opposite phases to each other and having an identical frequency with each other. Practically, the shift register 11 is controlled by a shift clock .phi.1 and an inversion signal thereof .phi.1. The shift register 12 is controlled by a shift clock .phi.2 and an inversion signal thereof .phi.2. The shift register 13 is controlled by a shift clock .phi.3 and an inversion signal thereof .phi.3. The shift register 14 is controlled by a shift clock .phi.4 and an inversion signal thereof .phi.4. There is a delay between the phases of the shift clocks corresponding to two adjacent sampling analog switches (for example, the shift clocks .phi.1 and .phi.2 corresponding to the sampling analog switches 21 and 22), the delay being 1/8 of the period .tau.0 of the shift clock. In other words, the phase of the shift clock .phi.2 is delayed from the shift clock .phi.1 by 1/8 of the period .tau.0 of the shift clock. In this way, the phases of pairs of the shift clocks and the inversion signals .phi.1, .phi.1 to .phi.4, .phi.4 are sequentially delayed by 1/8 of the period .tau.0 of the shift clock. Accordingly, sampling analog switch control signals SR1 to SRn, which are outputs of the shift registers 11 to 14, have waveforms which are also sequentially delayed by 1/8 of the period .tau.0 of the shift clock. The sampling analog switches 21 to 2n are conductive while the sampling analog switch control signals SR1 to SRn are at the active or "ON" level, respectively. During the period .tau.0 when the sampling analog switches 21 to 2n are conductive, a video signal Video is sampled by the sampling analog switches 21 to 2n and retained in the sampling capacitors 41 to 4n. More particularly, the sampling capacitors 41 to 4n retain the voltage of the video signal Video which is held when the sampling analog switches 21 to 2n are switched OFF.
Due to the above-mentioned operation, although the sampling analog switch control signals SR1 to SRn are sequentially delayed in the same manner as in a source driver having only one shift register, the period .tau.0 of the shift clock can be four times larger than the shift pulse width in the source driver having only one shift register. Thus, the shift registers 11 to 14 can be operated at a low speed.
The above-mentioned source driver, however, has the following problem. The periods in which the sampling analog switch control signals SR1 to SRn are at the ON level are delayed by 1/8 of the period .tau.0 of the shift clock. That is, the periods are partially overlapped with each other. Accordingly, eight such signals, for example, SR1 to SR8 are simultaneously at the ON level. Thus, eight sampling analog switches 21 to 28 are simultaneously conductive, causing the video signal Video to be simultaneously supplied to the eight sampling capacitors 41 to 48 through the eight sampling analog switches 21 to 28. The source driver functions in the same manner concerning eight sampling analog switch control signals SR2 to SR9. As a result, the video signal line 30 or a circuit section for outputting a video signal Video is constantly loaded with the capacitance of the eight sampling capacitors 41 to 48. The capacitance and the wiring resistance of the video signal line 30 form an RC integrating circuit. The RC integrating circuit deteriorates the response of the sampling capacitors 41 to 4n to the video signal Video, and thus the waveforms of the video signal Video are distorted in the sampling capacitors 41 to 4n. The video signal Video having such distorted waveforms does not retain band data which was inputted thereto in, for example, a liquid crystal display apparatus. An image which is formed based on such a video signal Video has a low horizontal resolution.